1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same, and more particularly to a semiconductor device and a manufacturing method of the same, wherein: an interlayer insulation film is provided with a contact hole, a via hole, or with a trench designed for a buried wiring; and, the contact hole, the via hole, or the trench designed for the buried wiring is filled with copper or a copper-base conductive material through a barrier metal film of a tantalum-base metal to form a plug electrode or the buried wiring.
2. Description of the Related Art
In semiconductor devices typified by large scale integrated circuits (LSIs) such as memories, microprocessors and the like, the more the devices increase in integration density, the finer in dimension, and, therefore finer their dimension in their individual semiconductor regions forming various elements. Further, in forming a plug electrode or a buried wiring in each of these semiconductor regions, a contact hole, a via hole, or a trench designed for a buried wiring formed in the interlayer insulation film becomes finer in diameter. In addition, since the wiring density increases, a so-called multilevel interconnection technique for producing a multi-layer wiring stacked in the width direction of a semiconductor substrate has been developed.
The great majority of such LSIs is of MOS (Metal Oxide Semiconductor) type, which is constructed of MOS type transistors. Such MOS type LSI is hereinafter referred to simply as the LSI. In such LSI, more particularly, in the LSI which is high in processing speed, when a plug electrode or a buried wiring is formed in a contact hole, a via hole, or a trench designed for such buried wiring, a resistance of the wiring becomes a problem in operation. Due to this problem, a wiring having a small resistance is required. FIG. 16 is a characteristic graph, which outlines the relationship between a width of the wiring, i.e., wiring width (graduated on an x-axis of the graph) and a resistance of the wiring, i.e., wiring resistance (graduated on a y-axis of the graph). In this drawing, the wiring resistance is inversely proportional to the wiring width. Incidentally, in the same drawing, a characteristic curve indicated by a dotted line shows a processing speed of the LSI.
Heretofore, as a wiring material designed for the semiconductor device including the LSIs, an aluminum-base metal containing aluminum as its major component has been used. This type of aluminum-base metal has a resistivity of from 2.8 to 3.0 μΩcm. However, as long as the wiring is made of such aluminum-base metal, the LSI is restricted in processing speed within narrow limits which depend on the resistivity of the aluminum-base metal. Consequently, in order to improve the LSI in processing speed, it is necessary to use, as a material of the wiring, a conductive material smaller in resistivity than the aluminum-base metal. From the above standpoint, in place of such aluminum-base metal, copper (i.e., Cu) has been used. Copper has a resistivity of from 1.9 to 2.2 μΩcm, which is much lower than that of the aluminum-base metal.
Next, an example for forming a buried wiring with the use of copper will be described. In this example, an interlayer insulation film, which is made of silicon oxides (for example, such as SiO2 and the like) and provided with a trench designed for a buried wiring, is previously formed on a semiconductor substrate. Then, a copper thin film is formed on such semiconductor substrate by a sputter process and like processes. Subsequent to this, a copper thick film is formed on the copper thin film by plating. The reason why the copper films are formed in two stages is that it is necessary to form a copper wiring with a sufficient film thickness within a fine contact hole.
On the other hand, after completion of formation of these copper films, the semiconductor substrate is subjected to a heat treatment. In this heat treatment, a phenomenon that copper diffuses into the interlayer insulation film occurs.
As a result, many disadvantages are brought about by the above diffusion of copper into the interlayer insulation film. For example: the interlayer insulation film becomes poor in insulation properties; the wiring resistance increases; and, the wiring tends to break. In order to remove the above disadvantages, a barrier metal film is previously formed on the interlayer insulation film, and then copper is applied onto this barrier metal film to prevent the copper thus applied from diffusing into the interlayer insulation film.
For example, disclosed as such barrier metal film in the applicant's cited literature “International Reliability Physics Symposium 1997 Tutorial Notes, Pages 3.30-3.32” is a high melting-point metal film made of tantalum-base metal such as tantalum silicon nitride (TaSiN), tantalum nitride (TaN) and the like. The barrier metal film made of the tantalum-base metal has the excellent properties of being stable in adverse environments where the semiconductor device such as the LSIs and the like is used and subjected to wide temperature variations.
Next, problems to be solved by the present invention will be described. The tantalum-base metal as the barrier metal film disclosed in the above literature is poor in adhesion to a copper wiring formed thereon, which increases the tendency of the copper wiring to peel off, and, therefore decreases the reliability of the semiconductor device such as the LSIs and the like.
In other words, in forming the copper wiring, as described above, immediately after being formed, the copper films have an unwanted hillock or bump portion of its copper thick film surface subjected to a CMP (i.e., Chemical Mechanical Polishing) process to polish away such unwanted lump portion. At this time, the copper film tends to peel off. The reason why the copper film tends to peel off seems to be that an abrasive liquid used in the above CMP process passes through a low-adhesion or gap portion of the semiconductor wafer to enter the interior of the wafer, so that a connection portion of the copper wiring with the barrier metal film is eroded. Due to this, the wiring has a large resistance. Further, the semiconductor device provided with such barrier metal film becomes poor in resistance to both stressmigration and electromigration.
FIG. 17 is a schematic characteristic graph representing the relationship between the wiring width and the wiring resistance, obtained in the conventional semiconductor device. As is clear from this graph, as the wiring width decreases, the wiring resistance steeply increases.
The reason why adhesion between the tantalum-base metal and the copper wiring is poor seems to be that the tantalum-base metal formed by a sputter process and like processes receives no aftercare. Due to this, a stress occurs in the copper wiring—far more than in the tantalum-base metal, which leads to a peeling-off phenomenon of the copper wiring.
Further, in the above-mentioned conventional technique, adhesion between the tantalum-base metal and an interlayer insulation film disposed thereunder is also poor. The reason why it is so seems to be the same as that of the above.